Digital logic circuits often rely on clock signals for synchronization, derivation of reference signals, measuring phase differences, and other functions. The circuits may be segregated into different integrated circuits or different subsystems of a larger electronic device.
One approach for getting the clock signal to all components requiring a clock is to distribute the clock signal from a centralized clock to every component requiring the clock signal. One disadvantage of this approach is that clock signals tend to have constraints that are difficult to maintain when the distribution is over a relatively large area or used to drive a relatively large number of components.
Another technique for distributing a clock signal entails distributing a reference clock signal to different components or even different regions within an integrated circuit. Each component or region has a local phase locked loop (PLL) or local delay locked loop (DLL) buffer to derive one or more local clock signals from the reference clock signal. Such designs are sometimes referred to as a “clock tree”. The use of a tree structure allows clocked buffers to be configured for the specifics of the loads they are driving as well as limiting the load to be driven by any clock signal.
FIG. 1 illustrates one embodiment of a prior art PLL circuit 100. The reference clock 160 is provided to the reference clock input 112 of a phase comparator 110. The PLL clock output 180 is taken from the output of a variable frequency oscillator (VFO) 130. A feedback loop 170 couples the PLL clock output to a feedback input 114 of the phase comparator. The phase comparator generates a phase error signal which is filtered by a low pass filter (LPF) 120. The filtered phase error signal controls the VFO. The frequency and phase of the VFO varies in response to the filtered phase error signal. Driver 140 receives the output of VFO 130. VFO 130 is driven to cause the PLL clock output to match the phase and frequency of the reference clock. The PLL may be fabricated on a semiconductor substrate 150. Although only the monitored output 180 is shown, the PLL may drive multiple outputs.
A zero phase delay between the PLL clock output and the reference clock is often a design objective. However there are applications in which the designer needs the PLL clock output phase to lead the reference clock. Prior art clock PLL implementations introduce elements into the PLL feedback loop or select the load driven by the monitored output to change the frequency and phase relationship between the reference clock and the derived clock. Changing the amount of phase advance thus requires selecting different components for the PLL feedback loop or adjusting the load of the monitored output in such a prior art architecture.